The present invention is related to a drive circuit of a voltage driving type semiconductor element which is employed in a power converter, and also related to an inverter apparatus.
Voltage driving type semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) have a large number of such merits that drive circuits thereof can be made compact and can be operated with low losses, as compared with current driving type semiconductor elements such as thyristors. FIG. 10 is a structural diagram of a single-phase inverter with employment of power MOSFETs as the above-described voltage driving type semiconductor elements.
In the structural diagram of FIG. 10, the single-phase inverter has been equipped with power MOSFETs “M1” to “M4”, diodes “D1” to “D4” which have been built in these power MOSFETs “M1” to “M4”, a power supply voltage “Vin”, and an inductor 14 which constitutes a load. Drive circuits “G1” to “G4” have been connected to the above-described power MOSFETs “M1” to “M4”, respectively, the detailed circuit arrangement of which is shown in FIG. 11.
In FIG. 11, a drive circuit 1 is arranged by a DC power supply “Vdd”, a logic circuit, p-type channel MOSFETs “PM1” to “PM3”, and n-type channel MOSFETs “MN1” to “NM3.” Since a gate capacitance of the power MOSFET “M1” is large, a PWM signal is amplified by the CMOSFETs “PM1” to “PM3” and “NM1” to “NM3”, which constitute a buffer, and then, the amplified PWM signal drives the gate of the power MOSFET “M1.” The logic circuit contains a function capable of shutting down the drive circuit 1 when the voltage of the DC power supply “Vdd” is lowered; a function capable of preventing shortcircuits of upper and lower arms; a function capable of protecting the power MOSFET “M1” from an overvoltage and an overcurrent; and the like.
In the case that the power MOSFET “M1” is turned ON, the P-type channel MOSFET “PM3” employed in a final output stage of the drive circuit 1 is turned ON, and the n-type channel MOSFET “NM3” of this final output stage is turned OFF, so that a voltage at the gate of the power MOSFET “M1” is increased to the voltage of the power supply “Vdd.” On the other hand, in the case that the power MOSFET “M1” is turned OFF, the p-type channel MOSFET “PM3” employed in the final output stage of the drive circuit 1 is turned OFF, and the n-type channel MOSFET “NM3” of this final output stage is turned ON, so that a voltage at the gate of the power MOSFET “M1” is lowered to a potential at the source thereof.
However, in an actual circuit, as represented in FIG. 12, stray resistances “Rs1” to “Rs3”, and stray inductances “Ls1” to “Ls3” are present, which are caused by package and wiring lines of a circuit board. As a result, while switching operation of the power MOSFET “M1” is carried out, the gate voltage of the power MOSFET “M1” is shifted from the DC voltage of the power supply “Vdd” when the power MOSFET “M1” is turned ON, or shifted from the source voltage when the power MOSFET “M1” is turned OFF.
If the drain voltage is increased under such a condition that the power MOSFET “M1” is turned OFF, then a capacitance “Cgs” between the gate and the source of the power MOSFET “M1” is charged via another capacitance “Cgd” between the gate and the drain thereof, so that the gate voltage is increased. When the increased gate voltage exceeds a threshold voltage, the power MOSFET “M1” is erroneously ignited, namely turned ON. If the stray resistances “Rs1” to “Rs3” and the stray inductances “Ls1” to “Ls3” are sufficiently small, then a variation of the gate voltages is small, so that the erroneous ignition of the power MOSFET “M1” may be suppressed. Also, even when the drain voltage of the power MOSFET “M1” is gently increased, a variation of the gate voltages is small, so that the erroneous ignition of the power MOSFET “M1” may be suppressed.
Next, a description is made of a mechanism why erroneous ignition occurs while an inverter is driven with reference to FIG. 13 and FIG. 14. In FIG. 13, while the power MOSFETs “M1”, “M2”, “M3” have been turned OFF and the power MOSFET “M4” has been turned ON, a current is circulated through a path formed by the diode “D2”, the inductor 14, and the power MOSFET “M4” (namely, status of mode 1). In FIG. 14, the power MOSFET “M1” is turned ON; a current flows through the power MOSFET “M1”, the inductor 14, and the power MOSFET “M4” (namely, status of mode 2); and the voltage of the DC power supply “Vin” is applied to the inductor 14. If the power MOSFET “M1” is turned ON, then the voltage at the drain of the MOSFET “M2” is increased up to the voltage of the power supply “Vin.” However, since a stray inductance of a circuit is present, the voltage at the drain of the power MOSFET M2 becomes higher than or equal to the voltage of the power supply “Vin” in a transition manner. In this case, the gate voltage of the power MOSFET “M2” is increased via the capacitance “Cgd” between the gate and the drain of the power MOSFET “M2”, and if this increased gate voltage exceeds a threshold value, then the power MOSFET “M2” is erroneously ignited, so that a feed-through current flows through the power MOSFETs “M1” and “M2.”
FIG. 15 represents voltages “Vgs” between the gates and the sources of the power MOSFETs “M1” and “M2”; voltages “Vds” between the drains and the sources thereof; and drain currents “Id” thereof. In this case, the current of the built-in diode “D2” has been contained in the drain current “Id” of the power MOSFET “M2.” When the mode 1 (see FIG. 13) is selected, the gate voltages “Vgs” of the power MOSFETs “M1” and “M2” are zero, and the current is flowing through the diode “D2.” When the power MOSFET “M1” is turned ON (mode 2), the current flowing through the diode “D2” is lowered and the drain voltage “Vds” of the power MOSFET “M2” is increased. However, in this case, an increase “15” of the gate voltage “Vds” of the power MOSFET “M2” appears.
In order to suppress the above-described increase of the gate voltage, in conventional techniques, the below-mentioned means has been proposed (for instance, JP-A-2000-59189): That is, while a power supply having a negative voltage is employed, when a power MOSFET is turned OFF, the above-described means biases a gate thereof to become minus. However, since the power supply having the negative voltage is employed, there is such a problem that cost and a size of a drive circuit of an inverter are increased.
On the other hand, another means has been proposed (for example, JP-A-08-14976): That is, when a power MOSFET is turned OFF, the above-described means biases a gate thereof to become minus without employing the power supply having the negative voltage. However, in this conventional means, since a gate voltage applied when the power MOSFET is turned ON is decreased lower than a power supply voltage of a drive circuit, there is such a problem that an ON-resistance of this power MOSFET is increased, so that conduction loss thereof is increased.